1. Technical Field
The present invention relates in general to a logic switching circuit and in particular to a logic switching circuit providing an output waveform that switches between a lower rail voltage and an upper rail voltage. Still more particularly, the present invention relates to an improved logic switching circuit that provides an output waveform that switches quickly between a lower rail voltage and an upper rail voltage at low power supply voltages.
2. Description of the Related Art
A very large scale integration (VLSI) circuit of high performance having the advantages of both bipolar and metal oxide semiconductor (MOS) technologies may be realized by forming a bipolar transistor and a MOS transistor over a common semiconductor substrate and by placing these transistors in a circuit to form a so-called bipolar complementary metal oxide semiconductor (BICMOS). Typical BICMOS logic switching circuits include two different stages. The first stage includes CMOS field effect transistors (FETs) to achieve the desired logic function, while the second stage usually includes at least one bipolar transistor to operate as the driving stage of the logic switching circuit.
Bipolar transistors are known for their ability to supply higher currents than FETs under identical operating conditions. Additionally, bipolar transistors require less space and exhibit lower input capacitance than FETs. On the other hand, FETs are preferably utilized in the first stage of a BICMOS logic switching circuits to perform the desired logic function since FETs have superior integration density when low levels of power dissipation are required in the circuit. Moreover, FETs also provide better logic efficiency than the bipolar transistors.
Referring now to FIG. 1, a schematic diagram is depicted which illustrates a conventional prior art BICMOS logic switching circuit implementing a two input NAND function. In BICMOS logic switching circuit 100, transistors P1, P2, N1, N2, N3, and N4 provide the NAND logical function. Transistors P1 and P2 are p-channel FETs, while transistors N1, N2, N3, and N4 are n-channel FETs. Transistors T1 and T2 are NPN bipolar transistors that are connected in series with node 10 located between T1 and T2. Node 10 is the output node for this logic switching circuit.
Transistors P3, N5, P4, and N7 comprise the circuitry that provides a rail-to-rail output swing in the output of BICMOS logic switching circuit 100. A "rail-to-rail" output swing occurs when the output voltage shifts from a first voltage VDD to a second voltage GND or vice versa. Transistors P3 and P4 are p-channel FETs, while transistors N5 and N7 are n-channel FETs. Transistor N6 is an n-channel FET that ensures that T2 is off when T1 is on, allowing the output to shift from a first voltage GND to a second voltage VDD.
This conventional circuit provides a rail-to-rail output that switches quickly between the active bipolar region between a V.sub.BE from the lower rail to a V.sub.BE from the upper rail. The fact that the bipolar transistors, T1 and T2, do not remain in the active region throughout the entire rail-to-rail transition requires two small finishing FETs, P3 and N5, to complete the swing. These FETs also eliminate any potential DC power that would be dissipated by BICMOS logic switching circuits being driven by this circuit as a result of the output voltage swing of this circuit not being rail-to-rail.
The logic switching circuit depicted in FIG. 1 is adequate for operating voltages around 5 volts with a 1.0 micrometer BICMOS technology. For submicron technologies operating at supply voltages as low as 2.5 volts, however, this circuit topology becomes inadequate because the finishing FETs complete the rail-to-rail voltage swing too slowly. Submicron means less than 0.5 microns and submicron technologies include FET channel lengths less than 0.5 microns.
Therefore, it would be desirable to have a logic switching circuit topology that provides a quick rail-to-rail voltage response at low voltage levels.